1. Field of the Invention
Generally, the present disclosure relates to integrated circuits and methods for the manufacturing thereof, and, in particular, to integrated circuits including field effect transistors having gate electrodes including aluminum.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements which include field effect transistors and, optionally, other circuit elements such as capacitors, inductivities, diodes and resistors. The circuit elements in an integrated circuit may be electrically connected by means of electrically conductive metal lines formed in a dielectric material. The electrically conductive metal lines may be provided in a plurality of interconnect layers, and they may be connected to the circuit elements and to each other by means of contact holes and contact vias that are filled with metal.
Field effect transistors include an active region formed in a semiconductor material such as, for example, silicon. The active region includes a source region, a drain region and a channel region between the source region and the drain region, wherein a doping of the channel region is different from a doping of the source region and the drain region. Above the channel region, a gate electrode that may be separated from the channel region by a gate insulation layer may be provided. For increasing the capacity between the gate electrode and the channel region, high-k materials having a greater dielectric constant than silicon dioxide may be used for forming the gate insulation layer.
Furthermore, gate electrodes including one or more metals may be employed. The gate electrodes may include a workfunction adjustment layer over the gate insulation layer. A material of the workfunction adjustment layer may be adapted such that a workfunction of the gate electrode and a workfunction of the active region match. For N-channel transistors and P-channel transistors, different workfunction adjustment layers may be employed.
For forming field effect transistors including a gate insulation layer including a high-k material and a metal gate electrode, replacement gate techniques may be employed. In replacement gate techniques, dummy gate structures are formed over the channel regions of the field effect transistors. Adjacent the dummy gate structures, sidewall spacer structures may be provided, and ion implantation processes may be performed in the presence of the dummy gate structures and/or the sidewall spacer structures for forming source and drain regions. Additionally, an interlayer dielectric material may be deposited over the semiconductor structure.
Thereafter, a chemical mechanical polishing process may be performed for exposing the dummy gate structures. Then, the dummy gate structures of field effect transistors of a first type, for example the dummy gate structures of P-channel field effect transistors, may be removed, and materials of an optional replacement gate insulation layer, a workfunction adjustment layer and a gate electrode material may be deposited.
Thereafter, a chemical mechanical polishing process may be performed, and the dummy gate structures of the field effect transistors of the other type, for example the N-channel field effect transistors, may be removed. Then, layers of materials of an optional replacement gate insulation layer, the workfunction adjustment layer of the N-channel transistors and the gate electrode material may be deposited, and a chemical mechanical polishing process may be performed.
In the chemical mechanical polishing processes that are performed after the deposition of the materials of the gate insulation layers, the workfunction adjustment layers and the gate electrode material, portions of the deposited materials outside the recesses formed by the removal of the dummy gate structures are removed for forming replacement gate structures from portions of the deposited layers in the recesses.
Thereafter, a further layer of an interlayer dielectric may be deposited over the semiconductor structure, and contact holes may be formed therein. This may be done by means of techniques of photolithography and etching. The contact holes may include contact holes over the gate electrodes of the field effect transistors as well as contact holes over the source regions and the drain regions of the transistors. The contact holes may be filled with an electrically conductive material such as, for example, tungsten, for providing electrical contacts to the field effect transistors.
Using aluminum as the gate electrode material that is deposited over the workfunction adjustment layers of the transistors may have the advantage of providing a high electrical conductivity as well as a high charge carrier density of the gate electrode. However, providing electrical contacts to the aluminum of the gate electrodes may have some issues associated therewith.
The aluminum of the gate electrodes may have a layer of aluminum oxide on top of the aluminum. For providing an electrical connection to the aluminum, it is desirable to etch through the electrically insulating aluminum oxide layer in the formation of contact holes and to stop the etch process in the aluminum without forming an interfacial layer. Additionally, in the etch process used for removing the interlayer dielectric, etch polymers may be formed. After the etch process, such etch polymers may need to be removed in a “soft” manner, i.e., without attacking the aluminum, and without forming an interfacial layer so that a proper electrical contact to the aluminum of the gate electrodes can be established. However, sputter processes and/or wet chemical cleaning processes employed for removing etch polymers may have issues associated therewith, which may include an insufficient removal of etch polymers or, in the case of more aggressive cleaning processes, the cleaning processes may attack the aluminum. This may lead to very narrow process windows for cleaning processes employed for the removal of etch polymers. Issues as described above may occur, in particular, in the case of relatively large gate electrodes, wherein contacts are in contact with only the aluminum portions of the gate electrodes.
In semiconductor structures wherein gate electrodes including aluminum are provided, aluminum may also be used for the formation of elements other than gate electrodes such as, for example, lithography overlay marks or portions of circuit elements such as capacitors or inductivities. However, in chemical mechanical polishing processes, a dishing of relatively large areas of a semiconductor structure including aluminum may occur. Therefore, the possibility to form relatively large features of aluminum may be limited.
In view of the above-described situation, the present disclosure provides semiconductor structures and methods that may help to provide a better electrical contact to electrically conductive structures such as, for example, gate electrodes including aluminum. Furthermore, the present disclosure provides semiconductor structures and methods that may help to reduce a dishing of relatively large electrically conductive structures including aluminum in chemical mechanical polishing processes.